產(chǎn)品標(biāo)題:  UFC721AE 3BHB002916R0001 ABB控制板驅(qū)動板主板

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                                                   產(chǎn)品詳情資料：

3BHB002916R0001 UFC721AE

在步驟5中，傳輸編程后，設(shè)置DGCS中的GO位。如果由于PCI_CSR中的BM位未設(shè)置為啟用PCI總線主控權(quán)，或者源和目標(biāo)起始地址未對齊，DMA編程不正確，則將斷言P_ERR。否則，將設(shè)置ACT位，然后DMA將開始傳輸數(shù)據(jù)，與PCI目標(biāo)和中斷通道共享VMEbus的所有權(quán)，與VMEbus從屬通道共享PCI總線的所有權(quán)。在步驟6中，等待DMA傳輸?shù)慕K止。DMA將繼續(xù)傳輸，直到：?完成所有傳輸，?使用STOP_REQ位提前終止，或?在PCI總線或VMEbus上遇到錯誤。這些條件中的每一個都將導(dǎo)致ACT位清零，并在DGCS寄存器中設(shè)置相應(yīng)的狀態(tài)位。如果在步驟1中啟用，也將生成中斷。一旦軟件設(shè)置了GO位，軟件就可以通過等待中斷生成或輪詢狀態(tài)位來監(jiān)控DMA完成。建議還啟動后臺計時器以使傳輸超時。這將確保DMA沒有被繁忙的VMEbus或其他此類系統(tǒng)問題掛斷。

                                                  產(chǎn)品英文詳情料:

In Step 5, with the transfer programmed, the GO bit in DGCS must be set. If the DMA has been improperly programmed, either because the BM bit in the PCI_CSR has not been set to enable PCI bus mastership, or the source and destination start addresses are not aligned, then P_ERR will be asserted. Otherwise, the ACT bit will be set, and the DMA will then start transferring data, sharing ownership of the VMEbus with the PCI Target and Interrupt channels and the PCI bus with the VMEbus Slave Channel. In Step 6, one waits for termination of the DMA transfers. The DMA will continue with the transfers until it: ? completes all transfers, ? is terminated early with the STOP_REQ bit, or ? encounters an error on the PCI bus or VMEbus. Each of these conditions will cause the ACT bit to clear, and a corresponding status bit to be set in the DGCS register. If enabled in Step 1, an interrupt will also be generated. Once the software has set the GO bit, the software can monitor for DMA completion by either waiting for generation of an interrupt, or by polling the status bits. It is recommended that a background timer also be initiated to time-out the transfer. This will ensure that the DMA has not been hung up by a busy VMEbus, or other such system issues.

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